In the semiconductor manufacturing process, ensuring that every chip has good functionality and performance before leaving the factory is the key to ensuring product quality and customer satisfaction. Among them, CP testing (Circuit probing Test) is a key link in the semiconductor manufacturing process, mainly conducting electrical performance testing on chips at the wafer stage.
CP testing is a rapid detection of the circuit functions and parameters (such as voltage, current, frequency, timing, etc.) of each chip on the wafer by connecting the testing equipment to the wafer through a probe card, in order to screen out qualified chips. Due to the fact that testing is conducted at the wafer level, it is also known as wafer sorting or wafer testing.
The chip testing conducted by connecting the exposed chip to the testing machine through a probe on the entire wafer without wafer packaging is called CP testing.
Test object: All chips on the entire wafer (Die)
Testing timing: After the completion of wafer manufacturing (Front End), before packaging (Back End)
Test objective: To screen out chips with poor functionality or excessive parameters, avoid sending bad chips into the packaging process, thereby saving packaging costs and improving the yield of the final product.
After the completion of wafer production, various manufacturing defects introduced due to process reasons may result in a certain amount of defective products in the bare DIE distributed on the wafer. The purpose of CP testing is to identify these defective products (Wafer Sort) before packaging, thereby improving the yield rate at the factory and reducing the cost of subsequent packaging testing.
Yield monitoring and analysis: By analyzing the test results, the yield of each wafer is calculated to help the manufacturing department analyze the source of process defects; Identify the distribution of "bad pixels" on the wafer (such as edge failure, center failure, etc.) and optimize the manufacturing process.
Cost control: Packaging costs are much higher than wafer manufacturing costs. If defective chips are packaged, it will cause huge waves; CP testing can eliminate bad chips in advance and only package good chips (Known Good Die, KGD), significantly reducing overall costs.
Functional verification: Verify whether the basic functions of the chip are normal, such as digital logic, analog performance, memory read-write, I/O interfaces, etc; Detect manufacturing defects such as short circuits, open circuits, and leakage.
Parameter Test (DC/AC Test): Supply Current (IDD/IDDQ); Input leakage current (IIH/IIL); Output driving capability; Time sequence parameters such as clock frequency and setup/hold time; Measure key electrical parameters.
Provide data support for subsequent testing: CP test results can be used for speed binning, repair, or debugging in the FT (Final Test) phase.
And usually during chip packaging, some pins are encapsulated internally, resulting in some functions that cannot be tested after packaging and can only be tested in CP.
CP testing plays the role of a "quality gatekeeper" in semiconductor manufacturing, significantly improving production efficiency, reducing costs, and ensuring chip performance and reliability through early defect detection, process optimization, and resource allocation. As process nodes evolve towards smaller sizes (such as 2nm and below), the accuracy and speed requirements for CP testing will further increase, becoming a key factor in the competitiveness of the chip industry.

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